Low inductance interconnection of cryoelectric memory system

ABSTRACT

A length of flexible insulating material such as Mylar or Kapton having parallel conductors on one surface and including a magnetic field shield insulated from the conductors. The parallel conductors are connected at one end to lines at one edge of one cryoelectric memory plane and at the other end either to lines at the corresponding edge of the next adjacent plane, or to a terminal bar whose lines and shield are similar to that of the memory plane. The adjacent plane, in this case, is also connected to the terminal bar but via a second connector such as described. The shield comprises side-by-side diescrete conductive sections insulated from one another, each section registering with, that is, lying under (or over) a pair of conductors. Each adjacent pair of conductors is driven in such manner that one carries current in one direction and the other &#39;&#39;&#39;&#39;simultaneously&#39;&#39;&#39;&#39; carries an equal amount of current in the opposite direction.

United States Patent [72] Inventor [21 Appl. No. [22] Filed [45] vPatented [73] Assignee Robert A. Grange Belle Mead, NJ. 784,019

Dec. 16, 1968 May 18, 1971 RCA Corporation [54] LOW INDUCTANCEINTERCONNECTION OF CRYOELECTRIC MEMORY SYSTEM 9 Claims, 7 Drawing Figs.52 use: 340/1734, 339/17, 340/173,'340/174 51 110.01 Gllc5/06, H05k 7/06501 FieldofSearch 340/1731.

174(MA); 339/(lnquired), 17 (F), 19, 143; l74/(lnquired), 36, 88, l 17.]l

CRYOGENIC ASSOCIATIVE PROCESSOR PLANES;

Technical Report No. RADC-TR-65-74; Rome Air Development Center,A.F.S.C., Griffis A.F.B., N.Y.; May 1965; pp. 27 35 (340/l73.1)

Kahan, SUPERCONDUCI'IVE INTERPLANE COUPLER, IBM Technical DisclsoureBulletin, Vol. 3 No. 10; March 1961;p. 117 (340/l73.l)

Primary Examiner-Terrell W. Fears Attorney-H. Christoffersen ABSTRACT: Alength of flexible insulating material such as Mylar or Kapton havingparallel conductors on one surface and including a magnetic field shieldinsulated from the conductors. The parallel conductors are connected atone end to lines at one edge of one cryoelectric memory plane and at theother end either to lines at the corresponding edge of the next adjacentplane, or to a terminal bar whose lines and shield are similar to thatof the memory plane. The adjacent plane, in this case, is also connectedto the tenninal bar but via a second connector such as described. Theshield comprises side-byside diescrete conductive sections insulatedfrom one another, each section registering with, that is, lying under(or over) a pair of conductors. Each adjacent pair of conductors isdriven in such manner that one carries current in one direction and theother simultaneously" carries an equal amount of current in the oppositedirection.

LOW INDUCTANCE INTERCONNECTION OF CRYOELECTRIC MEMORY SYSTEM BACKGROUNDOF THE INVENTION In the hybrid cryoelectric memory system described inarticles by the present inventor, Taking Cryoelectric Memories out ofCold Storage, Electronics, Apr. 17, 1967, p. Ill, and CryoelectricHybrid System for Very Large Random Access Memory," Proceedings of theIEEE, Oct. 1968, p. 1967, the a lines and also the d (sometimes alsoknown as s) lines are serially connected from plane to plane of a stackof planes. These lines are relatively long and the time delay theyintroduce is significant compared to the width of the pulses employed todrive the lines. This delay is equal to the line length divided by thevelocity with which a signal propagates down the line. It is thereforeclear that one way of achieving relatively low memory access and cycletimes for a fixed electronics cost is to increase as much as possiblethe signal propagation velocity.

In many electrical signal transmission systems, the per unit lengthinductance and capacitance of the transmission line along which thesignal propagates is a constant. This is not the case with thecryoelectric memory system dealt with in the present application. Here,the interconnections among the planes of the stack introduce periodicinductance and capacitance discontinuities. One researcher, Dr. A. R.Sass, formerly of RCA Laboratories, has calculated that the propagationvelocity v along a line such as an a line of a cryoelectric memory isive) ear" where It is clear from equations (1) and (3) above that if themagnitude of the ratio of interconnecting inductance to memory planelength is comparable to the per unit length inductance of the a stripwhich lies over the memory plane, the signal propagation velocity willdecrease and the cycle time will increase correspondingly. While thisproblem has been recognized for a considerable period, there has been nopractical solution to it up to the present time and the object of thisinvention is to provide such a solution.

so that SUMMARY OF THE INVENTION The connector of the inventioncomprises a length of flexible insulating material having 2n parallelconductors and including also a magnetic field shield insulated from theconductors. The magnetic field shield comprises n discrete sections,each registering with, that is, lying under (or over) a pair of adjacentconductors.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a broken-away perspectiveview of portions of two memory planes and a portion of a connectoraccording to one form of the invention joining the two planes;

FIGS. 2a and 2b are top and bottom views, respectively, of the connectorof FIG. 1;

FIG. 3 is a cross section taken at an edge of a memory plane showing howthe connector is joined to the plane;

FIG. 4 is an exploded schematic showing of two stacks of memory planeswith the planes of each stack interconnected in accordance with thepresent invention;

FIG. 5 is a perspective showing to help explain how the interconnectionmeans of the invention achieves a reduction of interconnectioninductance; and

FIG. 6 is a cross section through a modified form of connectingstructure according to the invention.

DETAILED DESCRIPTION The memory system to be described is operated at alow temperature such as that of the order of liquid helium temperature.As the means for achieving such an environment is now well understood inthe art, it is not illustrated or discussed further.

Two memory planes of a stack of such planes are shown, in part, inFIG. 1. Details of the planes are given in the articles mentioned aboveand in a copending application by the present inventor and Peter Hsieh,application Ser. No. 736,341 for Line Terminating Circuits, filed June12, I968. In brief, each memory plane comprises a glass substrate 10 onwhich a lead ground plane 12 is formed. A layer of insulation 14, suchas one formed of silicon monoxide, is over the ground plane and thesense lines s, two of which are shown at 16, are located over thislayer. The next layer 18 is also insulation and there are additionallines, b lines, two of which are shown at 20 on this insulation layer.The final insulation layer is 22 and the a lines 24 are present on thislayer. The sequence of the a, b lines is somewhat arbitrary, and theorder shown in FIG. 1 is chosen for reasons of clarity. In addition, theb lines 20 are at all times orthogonal to the s lines; they appear asshown, however, for reasons of clarity.

The interconnection structure of the present invention is showngenerally at 26. It comprises a length of flexible insulating material28 such as Mylar or Kapton. Mylar is a trade name for a polyethyleneterephthalate insulating film and Kapton is a trade name for a polyimideinsulating film. Both names are trademarks of Dupont and both productsare commercially available. Parallel conductors, four of which, 29-1,29-2, 29-3 and 29-4 are shown, are located on one surface of theinsulating material 28. A magnetic field shield comprising discreteconductive sections, two of which are shown in part at 30 and 32, areshown located on the opposite surface of the insulation material 28.However, they may also be located on the same side of 28, provided, ofcourse, that the shield sections are insulated from the conductors. Eachshield section is insulated from the adjacent section and is of theshape of an elongated 0 that is, it is formed with a central opening.The longer legs, such as 30a and 30b, of each shield section, registerwith, that is, they lie directly beneath the corresponding conductors29-1 and 29-2 on the opposite surface of the insulating member 28. Theconductors and shield are formed of a superconductor such as lead.

The parallel conductors 29 are connected at one end to the a conductorson one plane and are shown connected at the opposite end to the aconductors on the immediately adjacent plane. For example, conductor29-1 is connected at one end to the a conductor 24-1 and is connected atits opposite end to the corresponding end of the a conductor 24-la, onlythe end of which is visible on the next adjacent plane 10a. Note thatthe adjacent plane may be replaced with a terminal bar which may serveas a convenient disconnect interface between two adjacent memory planes,the ends of which both connect to opposite sides of the terminal bar;the key requirement here is that the conductors and shield of theterminal bar appear as that of a memory plane to the flexibleinterconnecting structure.

The connecting structure is shown more clearly in FIGS. 2a and 2b. Theparallel conductive strips 29-1, 29-2... 29-n on one surface are shownin FIG. 2a. The shielding means comprising sections 30, 32 and so on, onthe opposite surface of the insulating material 28, are shown in FIG.2b.

The more detailed showing of how the connection is made appears in FIG.3. The a line 24-1 is located, for the major portion of its extent, overthe ground plane 12. However, the 'end of each a line is terminated in aterminal 40 which is known as a landl This land 40 is fabricated bydepositing a metal layer each time a metal layer is deposited duringfabrication of the memory array. For example, when the lead ground plane12 is laid down, the lead region 40a of the land is deposited. When thenext metal layer, namely the s lines 16 of FIG. I are laid down, theregion 4017 of the layer is deposited. This region is made of tin, justas are the s lines. During the chemical etching which takes place aftereach deposition, region 40 (40a40b and so on) is protected by apolymerized photoresist so that it is not removed by the etchingchemicals. in this manner the land 40 is built up in successive layersto form a sturdy columnar structure solidly secured to the glasssubstrate and capable of being soldered to.

g The interconnecting structure-26 is shown only in part in FIG. 3. Theconductor 29-1 is soldered to the land 40, as shown. The conductiveshield section 30 preferably extends over the ground plane 12. 1 In theoperation of'the memory, care is taken to insure that current flowsinoneia line at the same time that current of an equal amount flows in theopposite direction in the next adcurrents flow in opposite directions intwo adjacent strips such as 29 and 29-(n-I) as shown in FIG. 5. Forpurposes of clarity of illustration, the insulating material 28 is notshown in FIG. 5 and the strips and shield are shown-to be flat ratherthan curved. 1

In response to the two drive current waves which propagate in theconductive strips 29 in the directions indicated by arrows 50 and 52 inFIG. 5, correspondingimage currents, indicated by arrows 54 and 56, flowin the shield section 58. These image currents flow substantiallyentirely .on the side of the shield section 58: facing the conductors 29thereby providing a magnetic field distribution which corresponds to aminimum in the free-energy of the structure. The return paths for theseimage curnents are relatively very short and are indicated by the dashedarrows 62 and 64.. For example, the conductors 29 may be 2 mils in widthand spaced 2 mils apart so that each return path is only 2 mils inlength. 'Except for these return paths, the shield section 58 acts'as aperfect magnetic field shield forthe magnetic energy of the conductors29 and since these conductors are much longer (of the order of 500 to1,000 mils) than the spacing between the conductors, the inductancethey-exhibit is extremely low. It should be re: called here thata-current-carrying conductor whose magnetic field is completely shieldedexhibits an extremely low inductance.

While not essential, it is preferablethat the end regions 66 and 68 ofthe shield sections be located over the ground planes {of the respectivememory planes as is illustrated in FIG. 3. The

reason is to provide additional magnetic field shielding for 'even thesevery small image return paths.

, The use of discrete shielding sections for the interconnection member26 rather than a continuous shield has a number tion. In contrast, if acontinuous magnetic field shield were employed for the interconnectionmember, there would be edge effects. The conductors close to the edgesof the member would exhibit a somewhat different value of inductancethan the conductors at the center of the member. This would bedisadvantageous as it would mean that the propagation velocity of thememory drive currents would be address dependent," that is, the timerequired to access one memory location could be different than thatrequired to access another memory location, especially since the efiectwould be cumula V tive over many planes.

It has also been found that the sectioned magnetic field shield, asshown, has an important mechanical advantage over the use of acontinuous shield. The latter is unduly stressed when cycled betweenroom temperature and liquid helium temperature and this stress canresult in crazing, cracking and/or other damage to the interconnectionmember. The use of discrete, spaced shielding sections prevents thisfrom occurring.

A memory system including the invention is illustrated schematically inFIG. 4. Only two of the hundreds or thousands of a drive lines areshown. Further, while for purposes of illustration, the planes are shownrelatively widely spaced from one another, in practice they lie adjacentto one another. The space between the planes is determined by packagingconstraints andmay be of the order of 250 to 500 mils.

The planes may be arranged in two groups of 16 planes each. The balanceddriver 70 supplies current to' and draws current from the two sets ofplanes throughthe baluns 72 to insure that equal and opposite currentwaves propagate along the two lines on each plane. The operation of oneform of balanced driver (shown in FIG. 4) is discussed in detail in thecopending application mentioned above. Terminating resistors are notshown for reasons of clarity and it is to be understood that many otherdriving arrangements are possible for obtaining drive currents such asdiscussed herein. Each pair of adjacent planes is-connected by aninterconnection element such as described in detail above. Each pair ofadjacent planes face in opposite directions. For example, the a lines onplane L-] are shown facing downwardly as viewed in FIG. 4, whereas the 0lines on plane L-2 are shown facing upwardly as viewed in .FIG. 4. The alines on the plane L-3 face downwardly, whereas the a lines on the planeL-2 face upwardly, and so on. FlG. 6 shows the arrangement mentionedbriefly above employinga terminal bar 81. The bar may comprise a lengthof glass 83 on which is deposited a sectioned or even a continuousground plane 85. Insulation 87 is located over the ground plane and aplurality of parallel conductors one of which is shown at 89, arelocated over the insulation. The ends of each conddctor are terminatedby a land, two such lands, these for the conductor 89 are shown at 89aand 89b. The ground plane ,and the parallel conductors 89 are preferablyformed of superconductive material such as lead.

The terminal bar 81 acts just like a memory plane from an electricalviewpoint, although its only function is to join the two connectors 26aand 26b. The conductors 29' connect at one end to the conductors 24 (notshown) of one memory plane and connect at their other end to therespective lands such as 8% of the parallel conductors of the terminalbar. The shield elements, one of which is shown at 30', are identical tothe shield elements already discussed and preferably extend over theground plane 85-of the tenninal bar at one end and over the ground plane(not shown) of the memory plane (not shown) at their other end. Theconnector 26b is connected between the terminal bar 83 and a secondmemory plane similarly to the connector 26a.

We claim:

1. An interconnection element for the conductive strips on two memoryplanes comprising, in combination:

a strip of flexible insulating material;

2n spaced, parallel. conductors on said strip; and

n discrete, spaced magnetic field shielding elements also on said stripand insulated from said conductors, each shielding'element registeringwith exactly one pair of adjacent conductors and insulated from theother shielding elements, where n is an integer greater than 1.

2. An interconnection element as set forth in claim I, wherein eachshielding element is of O-Shape and is formed with a central openinglying beneath the space between the two conductors registered with saidshielding element.

3. An interconnection element as set forth in claim 1,

wherein said shielding elements and conductors are formed ofsuperconductive material.

4. An interconnectionelernent as set forth in claim 2,

wherein said shielding elements and conductors are formed of 5superconductive material.

5. An interconnection element as set forth in claim I, wherein thespaced parallel conductors are on one surface of the strip of insulatingmaterial and the magnetic field shielding elements are on the oppositesurface.

6. ln combination:

two superconductor memory planes stacked one over the other and facingin opposite directions, each having at one surface thereof conductorsterminated at an edge of the plane by lands; and

an interconnection element for electrically connecting the two planes,said element comprising;

a length'of flexible insulating material;

a plurality, equal in number to the number of lands on a plane, ofparallel superconductive strips, each joined at one end to a land on oneplane and at the other end to a land on the other plane, said stripsbeing located on one surface of said insulating material; and

a plurality of shielding elements, insulated from one another, equal tohalf the number of lands on a plane, said shielding elements lying onthe opposite surface of said insulating material and each shieldingelement lying beneath a pair of adjacent superconductive strips.

7. In the combination set forth in claim 6, each shielding element beingin the shape of an elongated 0, one element of the 0 being of the samewidth as and lying immediately under one strip and another element ofthe O beingof the same 6 width as and lying underan adjacentstrip.

8. In the combination set forth in claim 7, each memory plane having aground plane and the lands on each plane extending beyond the groundplane, and each end of each elongated O-shaped shielding element lyingover and insulated from a ground plane. 1

9. in combination:

two superconductor memory planes stacked one over the other and facingin opposite directions, each having at one surface thereof conductorsterminated at an edge of the plane by lands;

two interconnection elements for electrically connecting the two planes,each said element comprising:

a length of flexible insulating material;

a plurality, equal in number to the number of lands on a plane, ofparallel superconductive strips, said strips being located on onesurface of said insulating material; and

a plurality of shielding elements, insulated from one. another, equal tohalf the number of lands on a plane, each such element on the oppositesurface of said insulating material and beneath a pair of adjacentsuperconductor strips; and

a terminal bar comprising an insulator, parallel conductors equal innumber to the number of lands on a plane on one surface of theinsulator, and a magnetic field shield on the other surface of theinsulator, the conductors on the respective interconnection elementsbeing connected at one end to the conductors of the tenninal bar and atthe other end to the lands of the respective memory planes.

1. An interconnection element for the conductive strips on two memoryplanes comprising, in combination: a strip of flexible insulatingmaterial; 2n spaced, parallel conductors on said strip; and n discrete,spaced magnetic field shielding elements also on said strip andinsulated from said conductors, each shielding element registering withexactly one pair of adjacent conductors and insulated from the othershielding elements, where n is an integer greater than
 1. 2. Aninterconnection element as set forth in claim 1, wherein each shieldingelement is of O-shape and is formed with a central opening lying beneaththe space between the two conductors registered with said shieldingelement.
 3. An interconnection element as set forth in claim 1, whereinsaid shielding elements and conductors are formed of superconductivematerial.
 4. An interconnection element as set forth in claim 2, whereinsaid shielding elements and conductors are formed of superconductivematerial.
 5. An interconnection element as set forth in claim 1, whereinthe spaced parallel conductors are on one surface of the strip ofinsulating material and the magnetic field shielding elements are on theopposite surface.
 6. In combination: two superconductor memory planesstacked one over the other and facing in opposite directions, eachhaving at one surface thereof conductors terminated at an edge of theplane by lands; and an interconnection element for electricallyconnecting the two planes, said element comprising; a length of flexibleinsulating material; a plurality, equal in number to the number of landson a plane, of parallel superconductive strips, each joined at one endto a land on one plane and at the other end to a land on the otherplane, said strips being located on one surface of said insulatingmaterial; and a plurality of shielding elements, insulated from oneanother, equal to half the number of lands on a plane, said shieldingelements lying on the opposite surface of said insulating material andeach shielding element lying beneAth a pair of adjacent superconductivestrips.
 7. In the combination set forth in claim 6, each shieldingelement being in the shape of an elongated O, one element of the O beingof the same width as and lying immediately under one strip and anotherelement of the O being of the same width as and lying under an adjacentstrip.
 8. In the combination set forth in claim 7, each memory planehaving a ground plane and the lands on each plane extending beyond theground plane, and each end of each elongated O-shaped shielding elementlying over and insulated from a ground plane.
 9. In combination: twosuperconductor memory planes stacked one over the other and facing inopposite directions, each having at one surface thereof conductorsterminated at an edge of the plane by lands; two interconnectionelements for electrically connecting the two planes, each said elementcomprising: a length of flexible insulating material; a plurality, equalin number to the number of lands on a plane, of parallel superconductivestrips, said strips being located on one surface of said insulatingmaterial; and a plurality of shielding elements, insulated from oneanother, equal to half the number of lands on a plane, each such elementon the opposite surface of said insulating material and beneath a pairof adjacent superconductor strips; and a terminal bar comprising aninsulator, parallel conductors equal in number to the number of lands ona plane on one surface of the insulator, and a magnetic field shield onthe other surface of the insulator, the conductors on the respectiveinterconnection elements being connected at one end to the conductors ofthe terminal bar and at the other end to the lands of the respectivememory planes.